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Description | Technology news, reviews, insights and leaks with a real technical twist, and the occasional rant or two... |
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h2 tags | Previewing China’s Loongson 3A5000 with Performance Counters Bulldozer, AMD’s Crash Modernization: Caching and Conclusion Bulldozer, AMD’s Crash Modernization: Frontend and Execution Engine Golden Cove’s Vector Register File: Checking with Official (SPR) Data Microbenchmarking AMD’s RDNA 3 Graphics Architecture AMD’s Zen 4, Part 3: System Level Stuff, and iGPU Golden Cove’s Lopsided Vector Register File Was Rocket Lake Power Efficient? Knight’s Landing: Atom with AVX-512 Cannon Lake: Intel’s Forgotten Generation AMD’s Zen 4, Part 2: Memory Subsystem and Conclusion AMD’s Zen 4 Part 1: Frontend and Execution Engine Microbenchmarking Nvidia’s RTX 4090 Why you can’t trust CPUID Addendum: Clock Ramp on ADL, Zen 4, M1, and More Microbenchmarking Intel’s Arc A770 Skylake: Intel’s Longest Serving Architecture Hot Chips 34 – Biren’s BR100: A Machine Learning GPU from China China’s Phytium D2000: Building on A72? Nvidia’s RTX 4090 Launch: A Strong Ray-Tracing Focus Hot Chips 34 – AMD’s Instinct MI200 Architecture How Quickly do CPUs Change Clock Speeds? Hot Chips 34 – Intel’s Meteor Lake Chiplets, Compared to AMD’s Hot Chips 34 – Tesla’s Dojo Microarchitecture Tachyum’s Revised Prodigy Architecture A Preview of Raptor Lake’s Improved L2 Caches AMD’s Athlon 64: Getting the Basics Right Caching Energy Efficiency Data – Mobile and AVX-512 Alder Lake’s Caching and Power Efficiency Tachyum: Too Good to be True? Intel’s Netburst: Failure is a Foundation for Success Sunny Cove: Intel’s Lost Generation Graviton 3: First Impressions iGPU Cache Setups Compared, Including M1 Examining Centaur CHA’s Die and Implementation Goals Centaur CHA’s Probably Unfinished Dual Socket Implementation Intel Renames Oregon Fab: Gordon Moore Park. Adds +270k sq ft, 18A Node now 2024 GPU Hardware Video Encoders – How Good Are They? VIA Part 4 – A Deep Dive into Centaur’s Last CPU Core: CNS SiFive Completes Series F Funding Round: +$175m, $2.5b Evaluation State of Windows on Arm64: a high-level perspective Going Armchair Quarterback on Golden Cove’s Caches Alder Lake’s Power Efficiency – A Complicated Picture Deep Diving Zen 3 V-Cache AMD’s V-Cache Tested: The Latency Teaser Intel’s Tremont: Atom Changes Course Gracemont: Revenge of the Atom Cores Alder Lake – E-Cores, Ring Clock, and Hybrid Teething Troubles Popping the Hood on Golden Cove Zhaoxin Part 3: A Sort of Anti-Climax Deep Diving Neoverse N1 Do IBM’s Giant L3 and V-Cache Represent the Future? The Weird and Wacky World of VIA Part 2: Zhaoxin’s not quite Electric Boogaloo Analyzing Video Card Efficiency, Part I – Power The Weird and Wacky World of VIA, the 3rd player in the “Modern” x86 market Details on the Gigabyte Leak Neoverse N1 vs Zen 2: ARM in Practice Measuring Zen 3’s Bottlenecks ARM or x86? ISA Doesn’t Matter How Zen 2’s Op Cache Affects Performance The End of an Era: AMD Discontinues Pre-2016 GCN GPU Support Nvidia’s Ampere & Process Technology: Sunk by Samsung? Exploring CPU Core to Core Latency and the Role that Locks Play GPU Memory Latency’s Impact, and Updated Test RDNA 1 Redux: Maximizing Performance With RX 5000 Series GPUs Measuring GPU Memory Latency Rocket Lake: When ‘Reviews’ are Really Previews Lowering the BAR: AMD’s 6700 XT launch and the Importance of Disclosure Modern Data Compression in 2021 Part 2 : The Battle to Dethrone JPEG with JPEG-XL, AVIF, and WEBP Analyzing Zen 2’s Cinebench R15 Lead A Patreon Story CTR Safety, Revisited Security and You, an Overview AMD’s Past and Future CPUs (Formal Retraction) CTR: A Review and a Warning (updated) Modern Data Compression in 2021 Part 1: A Simple Overview on the Art of Image Encoding Intel Finally Solving the Right Problem Intel’s HEDT Roadmap NVIDIA’s Next Generation GPU: MCM? NVIDIA’s Enterprise Welcome to Chips and Cheese Author |
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